Sunday, November 29, 2020

CMS-A-CC-3-5-TH: Computer Organization and Architecture Core Course- 5: Theory, Credits:04, Contact hours: 60.

 Basic Structure of Computers (Qualitative Discussion)

Computer Types, Basic Functional Units, Basic Operational Concept, Bus Structure,

Software, Performance, Multiprocessor and Multicomputer, IAS Computer, Historical

perspectives.

05 hours

Register Transfer and Micro-operation

Register Transfer Language, Register Transfer, Bus and Memory Transfers, Three State Bus

Buffers, memory Transfer, Arithmetic and Logical micro-operations, Shift and Arithmetic

shifts.

05 hours

Basic Computer Organization and Design

Instruction Codes, Stored Program Organization, Indirect Address, Computer Registers,

Common Bus System, Computer Instruction, Timing and Control, Instruction Cycle, fetch

Decode, Register Reference Instructions, Memory Reference Instruction, Input-Output and

Interrupt, Design of Basic Computer, Design of Accumulator Logic.

05 hours

CPU Organization

Arithmetic and Logic Unit (ALU)- Combinational ALU, 2'S Complement Addition,

Subtraction Unit, Booths Algorithm for Multiplication, Division Hardware using Restoration

Division Algorithm.

General register organization, Control Word, Accumulator Based, Register Based, Stack

Type CPU organization.

06 hours

Control Unit

Hardwired Control Unit, Micro-programmed Control Unit: Control memory, Address

Sequencing, conditional branching, mapping of instructions, subroutine, Design of Control

Unit.

07 hours

CPU Registers

Program Counter, Stack Pointer Register, Memory Address Register, Instruction Register,

Memory Buffer Register, Flag registers, Temporary Registers.

06 hours

Instructions.

Operational Code, Operands, Zero, One, Two and Three Address Instruction, Instruction

Types, Addressing modes, Data Transfer and Manipulation instructions, Program control

instructions.


CISC and RISC processors

Introduction, relative merits and De-merits.

03 hours

Computer Peripherals

VDU, Keyboard, Mouse, Printer, Scanner (Qualitative approach).

08 hours

Input / Output Organization

Polling, Interrupts, subroutines, Memory mapped IO, IO mapped IO, DMA, I/O Bus and

Protocol, SCSI, PCI, USB, Bus Arbitration.

02 hours

Memory

Primary memory: ROM, PROM, EPROM, EEPROM, Flash memory, RAM: SRAM,

DRAM, Asynchronous DRAMs, Synchronous DRAMs, Structure of Larger Memories,

RAMBUS Memory, Cache Memory: Mapping Functions, Replacement Algorithms,

interleaving, Hit and Rate penalty, Virtual memories, Address Translation, Memory

Management requirements, Secondary Storage: Magnetic Hard Disks, Optical Disks,

Magnetic Tape Systems.


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