CMS-A-CC-1-1-P: Digital Circuits Core Course-1: Practical, Credits - 02, Contact hours - 40.

 Combinational Circuits

1. Implementation of different functions (SOP, POS) using basic (AND, OR and NOT) logic gates.

2. Study and prove De-Morgan’s Theorem.

3. Realization of Universal functions using NAND and NOR gates.

4. Implementation of half (2-bit) and full adder (3-bit) using basic (AND, OR and NOT) and

Universal logic gates (NAND & NOR).

5. Implementation of half (2-bit) and Full Subtractor (3-bit) using basic (AND, OR and NOT) and

Universal logic gates (NAND & NOR).

6. Design and implement 1-Digit BCD adder using 7483/74283 and other necessary logic gates.

7. Design 4 to 1 multiplexer using basic or Universal logic gates and implement half and full

adder/subtractor.

8. Design and implement half and full adder /subtractor and other functions using multiplexers

74151/74153 and other necessary logic gates.

9. Cascading of Multiplexers.

10. Design 2 to 4 decoder using basic or universal logic gates.

11. Study 74138 or 74139 and implement half and full Adder/Subtractor and other functions.

12. 12. Implementation of 1-bit magnitude comparator using decoders (74138/74139) and other

necessary logic gates.

13. Cascading of Decoders.

14. Study magnitude comparators 7485.

15. Design and construct magnitude comparator (2-bit) using basic (AND, OR & NOT) and universal

(NAND/NOR) logic gates.

16. Design a display unit using Common anode or cathode seven segment display and decoders

(7446/7447/7448)

17. Design and implement 4-input 3-output (one output as valid input indicator) priority encoder

using basic (AND, OR & NOT) logic gates.

18. Study Priority Encoder IC 74147/74148.

19. Design a parity generator and checker using basic logic gates.

Sequential Circuits

1. Realization of SR, D, JK Clocked/Gated, Level Triggered flip-flop using basic or Universal logic

gates.

2. Conversion of flip-flops: D to JK, JK to D, JK to T, SR to JK, SR to D Flip-flop.

3. Design synchronous and asynchronous counters MOD-n (MOD-8, MOD-10) UP/ DOWN and

connecting Seven Segment Display along with decoder for display of counting sequence.

4. Construction of ODD/EVEN n-bit Synchronous Counter, where n is maximum 4.

5. n-bit binary arbitrary sequence synchronous counter where n is maximum 4.