CMS-A-CC-1-1-TH: Digital Logic Core Course-1: Theory, Credits-04, Contact hours - 60.

 Introduction to Computer fundamentals

Central Processing Unit (CPU), Primary and Secondary Storage devices, I/O Devices,

Classification of Computers: Super, Mainframe, Mini and Personal Computer, System and

Application Software.

Number Systems

Weighted and Non - Weighted Codes, Positional, Binary, Octal, Hexadecimal, Binary

Coded Decimal (BCD), Gray Codes, Alphanumeric codes, ASCII, EBCDIC, Conversion of

bases, 1's, 2's complement representation, Parity bits.

Single bit error detection and correcting codes: Hamming Code.

Fixed and Floating Point Arithmetic: Addition, Subtraction, Multiplication and Division.

Boolean Algebra

Fundamentals of Boolean Expression: Definition of Switching Algebra, Basic properties

of Switching Algebra, Huntington's Postulates, Basic logic gates (AND, OR, NOT), De-

Morgan's Theorem, Universal Logic gates (NAND & NOR), Minterm, Maxterm,

Minimization of Boolean Functions using K-Map up to four (4) variables, Two level and

multilevel implementation using logic gates, simplification of logic expressions.

Combinational Circuits

Adder & Subtractor:- Design and Construction of Half adders (2-bit) & Subtractor (2-

bit), Full Adder (3-bit) & Subtractor (3-bit) using basic logic gates (OR, AND, NOT) and

universal logic gates (NAND & NOR).

Multibit Adder:- Ripple Carry Adder, Carry Look Ahead (CLA) Adder, BCD Adder,

design & construct 1'S & 2'S Complement Adder/Subtractor unit using 4-bit full adder

units, 1-bit, 2-bit, 3-bit and 4-bit magnitude comparator using basic logic gates.

Data Selector-Multiplexer: Expansion (Cascading), function realization, Universal

function realization, Multifunction realization.

Encoders:- Realization of simple Encoders and priority Encoders using Basic and

Universal Logic gates.

Data Distributor:- De-multiplexer, Cascading, realization of various functions.

Chip Selector/Minterm Generator - Decoder- Function Realization, BCD Decoders,

Seven

Segment Display and Decoders.

Parity bit and Code Converters: Parity bit Generator/Checker, Gray to Binary code

converter, Binary to Gray Code Converter.

Sequential Circuits

Latch: Set/Reset (SR) using NAND and NOR gates, Gated S-R latches, D Latch, J-K

Latch, T Flip Flop, race around condition, Master-Slave J-K flip flop, Clock - Duty Cycle,

rising time, falling time, negative and positive edge detector circuits, edge triggered SR, D

and JK flip flop, flip-flop Conversions, flip-flops with preset/set and clear/reset

asynchronous inputs.

Registers: Serial Input Serial Output (SISO), Serial Input Parallel Output (SIPO), Parallel

input Serial Output (PISO), Parallel Input Parallel Output (PIPO), Universal Shift Registers.

Counters: Asynchronous Counter: UP/DOWN Counters, Mod - N Counters, BCD Counter

(Counter Construction using J-K and T Flip Flops).

Synchronous Counter: UP/DOWN Counters, Mod-N Counters, Ring & Johnson Counters.

Integrated Circuits (Qualitative study only)

Bipolar Logic Families: DTL, TTL NOT Gate, TTL NAND Gate, TTL NOR Gate, Open

Collector, Fan-in, Fan-out.

MOS Logic Families: NMOS, PMOS, CMOS, SSI, MSI, LSI and VLSI classification

(concepts only).