Computer Organization Question set 6

Chapter 6 – Control unit

1. Definition control unit

2. Hardwired control unit, micro programmed control unit advantages, disadvantages, comparison

3. State table method, sequence counter, delay element

4. Control memory

5. Wilkes design

6. Horizontal micro instruction, vertical micro instruction, comparison

7. Encoding of micro instruction

8. Parallelism in micro instruction 

Computer Organization Question set 5

                                 Chapter 5 – Instruction set

1. Instruction set

2. Instruction set completeness

3. Instruction format

4. Accumulator organization

5. Stack organization

6. Three address instruction, two address instruction, one address instruction, Zero address instruction

7. Addressing mode

8. CISC/RISC advantages, disadvantages, comparison

9. Instruction pipeline definition only

Computer Organization Question set 4

Chapter 4 – Memory

1. Defination – seek time, capacity, Rotational delay

2. Short note – memory hierarchy

3. SRAM – read and write technique

4. DRAM – Read and Write technique

5. SRAM,DRAM – Comparison

6. RAM CHIP, ROM CHIP example.

7. LARGE memory using small chip, range of memory address map

8. Memory -1D,2D,2.5D,3D

9. PROM, EPROM, EEPROM,FLASH MEMORY – Comparison

10. Magnetic Disc- track, sector, cylinder, inter-sector gap, surface, platter

11.  Short note- optical drive, associative memory

12. Cache memory- cache hit, cache miss, locality of reference, spatial locality, temporal locality, direct mapping, associative mapping, se-associative mapping, write through, write back, two level cache

13. Virtual memory

14. Page, frame

15. Page replacement technique.

16. Desructive and nondestructive memory

Computer Organization Question set 3

Chapter 3 - arithmetic

1.  Data representation –                                                                                 

a) sign magnitude

     b) 1‘s complement

     c) 2’s complement

   Advantages, disadvantages, comparison

      2. r‘s complement, r-1’s complement

      3.Floating point number representation (8 bit,32 bit,64 bit)

      4.Special cases of IEEE 754 format.

      5.1’s complement arithmetic,2’s complement arithmetic

      6.Overflow and underflow detection

      7.Algorithm or flowchart – a) fixed point addition-subtraction

                                                    b) add –shift   multiplication

                                                    c) Booth’s multiplication

                                                   d) restore and non-restore division  

                                                   e) floating point addition, subtraction,                                                                        multiplication, division

     8.Common bus system

     9.Tristate buffer

    10.parallel adder, cla, adder-subtractor, carry save multiplier

    11. Bit sliced ALU

    12. 4bit ALU design

Computer Organization Question set 2

Chapter 2 – instruction cycle

1. Instruction cycle

2. Fetch, decode, execute

3. MAR, MBR, PC, SP, IR, DR, Flag register

4. PSW

Computer Organization Question set 1

Chapter 1 - Introduction

1. Generation of computer, advantages, disadvantages

2. IAS computer structure, block diagram.

3. Von-Neumann concept.

4. Bottleneck of Von-Neumann.

5. Harvard architecture

6.Comparison of Harvard and Von Neumann.

Memory

Block diagram of ROM
Short note - PROM,EPROM,EEPROM
SRAM,DRAM
Comparison SRAM,DRAM
Read and write operation of Static ram cell
Read and write operation of Dynamic ram cell
Combinational circuit using ROM
Binary to ASCII using ROM
Full Adder using ROM
Block Diagram of PLA
Combinational circuit using PLA
Comparison ROM,PLA
Block Diagram of PAL
Combinational circuit using PAL
Comparison ROM,PLA,PAL

Sequential circuit using Mealy model and Moore model

Explain Moore type of sequential machine.
Explain Mealy type of sequential machine.
Compare Mealy model and Moore model
State transition,state diagram
Transition table
Rules of conversion
Design serial adder (ignoring carry)
Output=1 when even number of 1's accepted,otherwise output=0
Output=1 when 3k numbers of 1's accepted,otherwise output=0, k>=0
Output=1 when 3k numbers of 1's accepted,otherwise output=0, k>0
Output=1 when 3k+1 numbers of 1's accepted,otherwise output=0, k>=0
Output=1 when even number of 1's and even numbers of 0's accepted,otherwise output=0
Output=1 when even number of 1's and odd numbers of 0's accepted,otherwise output=0
Output=1 when odd number of 1's and even numbers of 0's accepted,otherwise output=0
Output=1 when odd number of 1's and odd numbers of 0's accepted,otherwise output=0
Output=1 when 1011 sequence accepted,otherwise output=0
Sequence generator

Register

Defination of register
Comparison of register and counter
Serial in serial out register
Serial in parallel out register
Parallel in serial out register
Parallel in parallel out register
Register with parallel load (SR,D,JK)
Shift register (Left - SR,D,JK)
Shift register (Right - SR,D,JK)
Bidirectional shift register
Universal shift register

COUNTER

Synnchronous counter - up- 2 bit,3 bit,4bit
Synnchronous counter - down- 2 bit,3 bit,4bit
Synnchronous counter - up- decimal,octal
Synnchronous counter - down- decimal,octal
Synnchronous counter - up/down 4 bit
Synnchronous counter - up- mod 3,mod 4,mod 6,mod 9,mod 10,mod 12
Synnchronous counter - down- mod 3,mod 4,mod 6,mod 9,mod 10,mod 12
Asynnchronous counter - up- 2 bit,3 bit,4bit
Asynnchronous counter - down- 2 bit,3 bit,4bit
Asynnchronous counter - up- decimal,octal
Asynnchronous counter - down- decimal,octal
Asynnchronous counter - up/down 4 bit
Asynnchronous counter - up- mod 3,mod 4,mod 6,mod 9,mod 10,mod 12
Asynnchronous counter - down- mod 3,mod 4,mod 6,mod 9,mod 10,mod 12
Ring Counter
Johnson Counter
Self stopping counter